Getting Started with BOLT

In order to address the ever increasing demands of IoT, we advocate a new architectural blueprint for the design of composable and predictable multi-processor wireless sensing platforms.

BOLT is an ultra-low power processor interconnect that decouples arbitrary application and communication processors with respect to time, power and clock domains. BOLT supports asynchronous message passing with predictable timing characteristics, and therefore making it possible for the system designer to construct highly-customized platforms that are easier to design, implement, debug, and maintain. The detailed design and extensive evaluation of BOLT is presented in the following research paper.

Follow the three steps outlined below to create your very own heterogeneous wireless sensing platform using the composable and predictable features of the BOLT processor interconnect.

 

STEP 1:  Select Your Processors

Select your application and communication processors according to your target application requirements. Example processors include the ARM Cortex-M4 and MSP430 CC430 SoC. Design files for BOLT-compatible adaptor boards are available for the CC430, STM32 and MSP432 development boards.

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STEP 2:  Construct Your Own BOLT

Create your very own BOLT using the design files and firmware. Load all the components, program the firmware using a JTAG programmer, and you’re ready to interconnect your processors!

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STEP 3:  Interconnect Your Processors

Interconnect your processors with BOLT with only negligible power overhead. Send messages asynchronously between application and communication processors using the example device drivers for the CC430, STM32 and MSP432 commercially-available development boards.

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Publications

Bolt: A Stateful Processor Interconnect
Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Federico Ferrari, Jan Beutel, Lothar Thiele
13th ACM Conference on Embedded Networked Sensor Systems (SenSys), November 2015

 

Demo: Building Reliable Wireless Embedded Platforms using the Bolt Processor Interconnect
Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Federico Ferrari, Jan Beutel, Lothar Thiele
13th ACM Conference on Embedded Networked Sensor Systems (SenSys), November 2015

 

Poster Abstract: Predictable Wireless Embedded Platforms
Felix Sutton, Reto Da Forno, Marco Zimmerling, Roman Lim, Tonio Gsell, Federico Ferrari, Jan Beutel, Lothar Thiele
14th ACM/IEEE International Conference on Information Processing in Sensor Networks (IPSN), April 2015